JEDEC vs. Intel DDR5 specs – timings tRRD_S, tRRD_L, tFAW and tRTP in benchmark tests with Alder Lake

1 - Premise and test methodology 2 - Activates (tRRD_S, tRRD_L, tFAW) in Theory 3 - Activates (tRRD_S, tRRD_L, tFAW) in Benchmarks 4 - tRTP / tRDPRE in Theory 5 - tRTP / tRDPRE in Benchmarks 6 - Summary and Conclusion

Activates (tRRD_S, tRRD_L, tFAW) declared

First, I was interested in the 3 “Activate Timings”, which should always be considered together because of their interdependencies. But what is an “Activate”? To understand this, all you really need to know is that RAM’s memory cells are organized into rows and banks, and these in turn are grouped together – Bank Groups. Those who read our DDR5 Deep Dive article will probably remember that DDR5 has 8 bank groups instead of 4, but that’s just by the by.

If now a memory address in a bank is to be accessed, its Bank Group must be activated. And the Activate Timings define how fast in succession these activations can take place. A distinction is made as to whether it is the same Bank Group as before or a different one. The former usually takes longer because the bank group still has to “recover” from the previous activation, which explains the naming of the timing, tRRD_L (long) or tRRD_sg (same group). Accordingly, tRRD_S (short) or tRRD_dg (different group) means that a bank is to be activated in a different bank group than before, which is usually faster.

Now it is only important that always 4 Activates can be executed one after the other. The Four Activate Window (tFAW) describes how long the time window for 4 Activates remains open at least. So it makes sense to dimension this timing with at least 4 * Min (tRRD_S, tRRD_L). If 4 Activates would take longer than tFAW, the window will still remain open and tFAW will effectively be extended. The timing therefore only describes a minimum duration, with which the RAM bank groups can still be given a “breather” after 4 activates. However, this is not necessary for most modern RAM ICs and the formula tFAW = 4* Min (tRRD_S, tRRD_L) is completely sufficient.

tRRD_S is defined in the JEDEC document for DDR5 so that this is at least 8 nCK, i.e. 8 clock cycles long. Thus, the actual duration can be calculated relatively simply as follows: For DDR5-4800, the actual clock rate is 2400 MHz as we know – DDR = Double Data Rate. 1 nCK thus corresponds to 1 s / 24000000 or also 4.16 e ^ -10 s. 8 times that is accordingly 3.328 e^-9 s or 3.328 ns. This mathematical exercise is still of a rather academic nature here, but it becomes much more important in the next timing.

tRRD_L is defined as a minimum value namely as 8 nCK (number of clock cycles) or 5 ns, whichever is greater. We already know from just now that 8 nCK with DDR5-4800 is 3.328 ns. Thus, the larger static value of 5 ns takes effect as the effective minimum according to the specification. So to find out which value would need to be set in bios, we can simply reverse the calculation. 5 ns / 0.416 ns (1 nCK for DDR5-4800) = 12.02. Since, of course, only integers can be set for the timings, the minimum for tRRD_L would be 13 for DDR5-4800 according to JEDEC.

On the contrary, Intel does not deal with effective time spans at all, but only specifies the number of clock cycles for the timings, namely 4 each for tRRD_S and tRRD_L and consequently 16 for tFAW. But which configuration brings the most performance with DDR5, JEDEC with 8/13/32, Intel with 4/4/16 or a completely different combination? The tests on the next page reveal it.