JEDEC vs. Intel DDR5 specs – timings tRRD_S, tRRD_L, tFAW and tRTP in benchmark tests with Alder Lake

1 - Premise and test methodology 2 - Activates (tRRD_S, tRRD_L, tFAW) in Theory 3 - Activates (tRRD_S, tRRD_L, tFAW) in Benchmarks 4 - tRTP / tRDPRE in Theory 5 - tRTP / tRDPRE in Benchmarks 6 - Summary and Conclusion

Today I want to talk about a guilty pleasure of mine, the overclocking of RAM, more precisely DDR5 and its timings. There is a strange difference between the specifications of JEDEC, the standard’s committee, and the Intel specifications of the Alder Lake CPUs of the 12th generation. And even though the exact functionality of the individual timings is probably a red flag for most people, it is still possible to draw a conclusion about their influence on the computing performance with simple comparison tests. And that’s exactly what we’re doing today.

Premise and methodology

Specifically, this article deals with the “Activate” timings tRRD_S, tRRD_L and tFAW, as well as the timing tRTP or tRDPRE. Here, as low as possible values mean as much performance as possible and accordingly the minimum value of the timings is of particular interest. However, this is exactly where the specification documents differ – while Intel specifies a minimum of 4 for the tRRD timings, for example, JEDEC specifies 8 or a timing equivalent of 7.5 nanoseconds, regardless of the clock rate. But what is true, which values actually still work and up to which point does the performance scale? The answers bring only tests, many many tests.

I’m using the Gigabyte Z690 Tachyon motherboard as an example, firstly because I’m still working on a review for it in parallel and secondly because almost all performance-relevant timings can be configured in the BIOS, which is unfortunately not a matter of course for all Z690 boards. CPU is an i9-12900K with 5.1 GHz on the P cores, 4.9 GHz on the E cores, disabled E cores and a microcode without AVX512, since I want to stick as close as possible to the officially supported specifications, also to exclude possible unforeseen interactions.

To illustrate the timings and their function, I refer to the documents from Intel and JEDEC, which I also only translate or interpret in the following. So if you prefer the unfiltered information, please go directly to the source I link here. While Intel’s documentation is freely available, you have to officially pay a few hundred USD to view the documents at JEDEC. Though experienced Googlers will certainly be able to find a copy in other ways.

To compare the computing performance, several synthetic benchmarks are used that are known to be particularly sensitive to RAM timings: Geekbench 3, SuperPi mod 1.5XS 32M, Linpack Xtreme 1.1.5 and Y-Cruncher 2.5b. To get the measurements even more consistent, Hyperthreading is disabled for SuperPi and a dedicated Linux-based operating system is used for Linpack Xtreme, which brings as little background noise as possible and should thus make the results even more reproducible. For the other tests, a Windows 11 image is used, which has been freed from most unnecessary background tasks, also to become at least a bit more consistent in the results. Of course, Windows 7 or Windows XP would be even more optimal for SuperPi, but this would have been beyond the scope of time and effort for now.

In addition, each benchmark was tested at least 3 times with each RAM setting and then averaged. This is the only way to draw truly reliable conclusions about the impact of the individual timings and to exclude other influences, at least to a large extent. If a result deviates too much from the previous average or obviously does not match the others, it is sorted out manually. All RAM timings are fixed manually for the tests, using relatively conservative and close to JEDEC timings. DDR5-4800 is used as the clock rate, as this is the highest with defined timing specifications in the version of the DDR5 documentation that I have access to. The following timings serve as baselines for the tests:

As always, the rest of the test hardware is still available as an overview: