KIOXIA EXCERIA PRO 2TB Review – BiCS5 has to compete with Micron’s 176-layer NAND, also in terms of price

1 - Einführung, Unboxing, Technik und Daten 2 - Teardown: Controller und NAND im Detail 3 - Dynamischer pSLC Cache im Detail 4 - Testsystem und synthetische Tests 5 - Anwendungsbenchmarks und Zusammenfassung

What does dynamic pSLC cache actually mean?

Now we come to a more technical detail, which most people might not be aware of to the full extent. Much has already been written about pSLC cache, so there is no need to go through it again in detail, at most as a small refresher. Here we go…

To increase the write speed, the so-called “pseudo-SLC cache” (pSLC) is often used in consumer products, although it can now also be found in various industrial solutions. For this purpose, part of the NAND capacity is configured as SLC memory, in which only one bit per cell is stored. Accordingly, this memory can be written and read very quickly. Since it is not dedicated, i.e. not a real SLC memory, it is called pseudo SLC. Such a cache can be used for all memory types that store several bits per flash cell, i.e. three bits as here with TLC. The pSLC cache also uses a significantly higher voltage for the one bit, which provides some security and is therefore better than Fast Page.

The use of pSLC cache offers a speed advantage, especially when the storage medium does not have read or write accesses between writing larger amounts of data. These idle times are used by the storage medium to move data from the cache to the TLC area.

But everyone knows the disadvantages of the pSLC. When the fast pSLC cache is full, the speed drops significantly because further write accesses to the storage medium must first free the pSLC by moving older data from the cache to the TLC memory. 

But what is hidden behind “dynamic pSLC cache”?  Dynamic pSLC cache has now also found its way into industrial storage solutions, but only with very hard restrictions. In contrast to the static pSLC cache, up to 100% of the NAND flash is used dynamically as pSLC cache, depending on how full the storage medium is. The cache can thus comprise up to 1/3 of the total memory size

However, the writing speed of the storage medium depends not only on the amount of data that is written without interruption, but also on the fill level of the memory. And this is exactly what makes the write speed in the life cycle difficult to predict.

NAND flash manufacturers do not recommend dynamically changing the configuration of flash blocks as pSLC or TLC memory for reliability reasons, but in the consumer sector, where the temperature windows are not so important, people are more relaxed about it.

All manufacturers of dynamic NAND storage media media, including Micron, permanently switch back to TLC mode after a specified maximum number of program and erase cycles. Before that, the storage medium achieves the best values especially in short write processes that do not require the entire capacity. After a certain amount of use, however, the medium slows down permanently, and this should never be ignored. Phison’s E18 handles dynamically changing the configuration of flash blocks quite well, but it can’t outsmart physics either.

It remains to be seen when the end of the cache performance will be reached. Real long-term tests will have to show that in the end, because unfortunately nothing is known about the Micron NAND yet. Thus, we gladly take note of the performance measured today, but also have to restrictively note that it will certainly be usable like this for longer, but never in the long run if you want to qualify as the write and delete king of large memory blocks.