KIOXIA EXCERIA PRO 2TB Review – BiCS5 has to compete with Micron’s 176-layer NAND, also in terms of price

1 - Einführung, Unboxing, Technik und Daten 2 - Teardown: Controller und NAND im Detail 3 - Dynamischer pSLC Cache im Detail 4 - Testsystem und synthetische Tests 5 - Anwendungsbenchmarks und Zusammenfassung

I had already written that the SSD gets a bit hotter since the older NAND has a higher power consumption and the heat dissipation should be really good. Once you have removed the labels, you can see the PCB, which this time does not come from TECHVEST, but was most likely manufactured by TECHVEST itself, because the corresponding UL entry on the PCB is missing and only the label refers to KIOXIA. And what do we see now? You can see the memory, the controller and the DRAM modules. But first things first, let’s start with the controller.

The controller used has been labeled as an OEM product from Phison on KIOXIA, but it actually hides the well-known PS5018-E18 behind it. This was developed from scratch by Phison at the time and is manufactured in TSMC’s 12 nm node. It is, in terms of features and performance, a very interesting and fast PCIe 4.0 x4 SSD controller. To realize this, Phison has included five Arm Cortex R5 CPU cores, three of which act as the primary cores for the main tasks, while the other two are clocked lower for the Dual CoXProcessor 2.0 code to act as a more economical tandem to take at least some of the load off the three main cores.

The controller communicates with the NAND via eight NAND flash channels at up to 1,600 MTps and supports capacities of up to 8 TB with 32 chip enable. However, you can see the bottleneck here, since BiCS5 can only deliver 1,066 MT/s and the controller cannot be nearly maxed out with that. This is then also the point that I meant at the beginning by contradiction.  The SSD contains four NAND modules on the top, thanks to the small size of the controller, which measures only 12 x 12 mm. The EXCERIA PRO’s design also uses a DRAM-based architecture, with two DDR4 chips from SK Hynix. These are two 2 GB CMOS Double Data Rate IV (DDR4 3200) Synchronous DRAM.

Phison’s PS5018-E18 complies with the NVMe 1.4 specification and has a number of common features. Thus, it supports both Trim and S.M.A.R.T.. Like other controllers, it uses Active State Power Management (ASPM), Autonomous Power State Transition (APST) and L1.2 ultra-low power state. Thermal throttling is implemented, but is of no further concern since the controller does not get too hot in most applications. This can also be seen in the fact that, unlike the older models like the E16, you can do without an integrated nickel heat sink.

It also leverages the fourth-generation LDPC ECC engine, SmartECC (RAID ECC), and end-to-end data path protection for robust error correction and improved data reliability. It even theoretically supports hardware-accelerated AES 128/256-bit encryption (which is TCG, Opal 2.0 and Pyrite compliant) and has a built-in crypto-erase feature, but the SSD does not advertise this. Phison’s E18, like the E12S and E16 models, supports fully dynamic write caching. The size of the dynamic pSLC cache, which I will also discuss in a moment, is therefore 1/3 of the available capacity of the TLC drive. Phison has also implemented SmartFlush, which enables fast cache recovery for predictable and consistent performance. So much for the theory. Well, not quite.

KIOXIAS BiCS5 NAND

The Phison PS5019-E19T just described is compatible with a wide range of flash memory variants and supports modern NAND chips with 1200 MHz interface. And because it is so nicely compatible, you can also use the older BiCS5 as a provider of a rather cheap NVMe SSD. The old BiCS4 still has 96 layers, so the number of layers has only increased slightly in the BiCS5. Flash Forward again relies on string stacking, so they simply combined two 56-layer arrays here. Flash Forward also promises up to 50% faster interface speed compared to BiCS4, well.

However, BiCS5 is primarily a way to significantly reduce costs. Through revised technology as well as improved manufacturing, the density of the cell arrays is said to have increased by 20 percent. Because the number of layers has also increased, the bit capacity per wafer is said to be 40 percent higher, which is why more chips with the same memory quantity can be cut from one wafer. The change from 96 to 112 layers should thus be cheaper than the change from 64-layer flash memory to those with 96 layers.

BiCS5 is not completely obsolete yet, but the BiCS6, which has been advertised for over a year, is actually the better product with its 162 layers (charge-trap technology) and the 1600 MT/s and is quite competitive to the current Micron NAND. However, only KIOXIA can answer itself why the older version is still used and BiCS6 cannot really be found.