CORSAIR MP600 PRO XT 2 TB NVMe SSD Review – Faster than the MSI SPATIUM M480?

1 - Einführung, Unboxing, Technik und Daten 2 - Controller, NAND und der dynamische pSLC Cache 3 - Synthetische Benchmarks 4 - Anwendungsbenchmarks und Zusammenfassung

I already wrote that you should better take off the stickers for a good performance, because the approx. 6 Watt peak (MSI SPATIUM M480 approx. 8 Watt) at maximum load want to be dissipated well on both sides. Once you’ve done that, you can see the PCB, which is again from TECHVEST, but has been customized for Corsair. Corsair’s MP600 Pro XT supports Active State Power Management (ASPM) and Autonomous Power State Transition (APST) to reduce power consumption when activity is low or the SSD is idle, so it only consumes a few milliwatts of power then.

A thermal throttling function is also integrated. The MP600 Pro XT lowers (throttles) its power when it gets too hot. Corsair states that for every additional degree of heat above the 68°C trigger point, the speed drops by 50 MBps. The SSD reached a maximum of 55 °C in the test, so there were no problems here. Of course, the SSD also supports Trim, SMART data reports, and can be securely erased with the Format NVM command to safely remove personal data from the drive. End-to-end data path protection and hardware-accelerated AES 256-bit encryption ensure data security.

Now let’s move on to the controller. Phison’s PS5018-E18 used was designed from scratch and is fabricated in TSMC’s 12nm node. It is, in terms of features and performance, a very interesting and fast PCIe 4.0 x4 SSD controller. To make this happen, Phison has included five Arm Cortex R5 CPU cores, three of which act as the primary cores for the main tasks, while the other two are clocked lower for the Dual CoXProcessor 2.0 code to act as a more economical tandem to take at least some of the load off the three main cores.

The controller communicates with the NAND via eight NAND flash channels at up to 1,600 MTps and supports capacities of up to 8 TB with 32 chips. Our sample contains eight modules, four on each side, thanks to the small size of the controller, which measures only 12 x 12 mm. The design also uses a DRAM-based architecture, with the MP600 PRO XT containing two DDR4 chips from SK hynix, one on each side of the PCB. These are each 1 GB modules, i.e. CMOS Double Data Rate IV (DDR4) Synchronous DRAM.

In the 2TB model we tested, there are 32 512GB flash chips in the form of Micron’s new 176-layer NAND (B47R), all running at the same 1,200 MTps speed. The chip installed is a quad-plane replacement gate architecture that uses metal-based control gates and several other design and manufacturing optimizations to increase performance and endurance. MSI still uses Micron’s 96-layer B27B on the SPATIUM M480. By the way, what happens when you remove the sticker while cold is shown in the next picture:

Phison’s PS5018-E18 complies with the NVMe 1.4 specification and has a number of common features. Thus, it supports both Trim and S.M.A.R.T.. Like other controllers, it uses Active State Power Management (ASPM), Autonomous Power State Transition (APST), and the L1.2 ultra-low power state (see datasheet page 1). Thermal throttling is implemented, but is of no further concern as the controller does not get too hot in most applications. This can also be seen in the fact that, in contrast to the older models such as the E16, you can do without an integrated nickel heat sink.

It also leverages the fourth-generation LDPC ECC engine, SmartECC (RAID ECC), and end-to-end data path protection for robust error correction and improved data reliability. It even supports hardware-accelerated AES 128/256-bit encryption (which is TCG, Opal 2.0, and Pyrite compliant) and has a built-in crypto-erase feature. Like the E12S and E16 models, Phison’s E18 supports fully dynamic write caching. The size of the dynamic pSLC cache, which I will discuss in a moment, is therefore 1/3 of the available capacity of the TLC drive. Phison has also implemented SmartFlush, which enables fast cache recovery for predictable and consistent performance. So much for the theory. Well, not exactly.

What does dynamic pSLC cache actually mean?

Let’s move on to a more technical detail that most people might not be aware of to its full extent. A lot has already been written about pSLC cache, there’s no need to go through it again in detail, at most as a little refresher. Here we go…

To increase the write speed, the so-called “pseudo-SLC cache” (pSLC) is often used in consumer products, although it can now also be found in various industrial solutions. For this purpose, part of the NAND capacity is configured as SLC memory, in which only one bit per cell is stored. Accordingly, this memory can be written and read very quickly. Since it is not dedicated, i.e. not a true SLC memory, it is called pseudo SLC. Such a cache can be used for all memory types that store several bits per flash cell, i.e. three bits as in the case of TLC here. The pSLC cache also uses a much higher voltage for the one bit, which provides some security and is therefore better than Fast Page.

The use of pSLC cache offers a speed advantage, especially when the storage medium does not have read or write accesses between writing large amounts of data. These idle times are used by the storage medium to move data from the cache to the TLC area.

But everyone knows the disadvantages of the pSLC. If the fast pSLC cache is full, the speed drops significantly, since further write accesses to the storage medium must first free the pSLC by moving older data from the cache to the TLC memory. 

But what is hidden behind “dynamic pSLC cache”?  Dynamic pSLC cache has now also found its way into industrial storage solutions, but only with very harsh restrictions. In contrast to the static pSLC cache, up to 100% of the NAND flash is used dynamically as pSLC cache, depending on how full the storage medium is. The cache can therefore comprise up to 1/3 of the total memory size

However, the writing speed of the storage medium depends not only on the amount of data that is written without interruption, but also on the fill level of the memory. And that’s what makes lifecycle write speeds difficult to predict.

Although NAND flash manufacturers advise against dynamically changing the configuration of flash blocks as pSLC or TLC memory for reasons of reliability, this is viewed in a more relaxed manner in the consumer sector, where the temperature windows are not so important.

All manufacturers of dynamic NAND memory media, including Micron, permanently revert to TLC mode after a specified maximum number of program and erase cycles. Prior to that, the storage medium achieves the best values especially for short write operations that do not require the entire capacity. However, after a certain amount of use, the medium slows down permanently, and you should never block that out. Phison’s E18 handles dynamically changing the configuration of flash blocks quite well, but it can’t outsmart physics either.

So it remains to be seen when the end of the great cache performance of the Spatium M480 will be reached. Real long-term tests will have to show that in the end, because unfortunately nothing is known about the Micron NAND. Thus, we gladly take note of the performance measured today, but must also restrictively note that it will certainly be usable like this for longer, but never in the long run. That’s why the Spatium M480 is especially recommended as an installation medium for large games and applications that don’t continuously write huge data blocks.