There have been (once again) new rumors about AMD’s RDNA 2 “Navi 2X” GPUs that will be found in the next generation graphics cards of the Radeon RX series. The rumor again points to a late start in the 4th quarter. It will be available in the second quarter of 2020 and will also cover RDNA 3, which could be a major revolution for the GPU market. The latest information comes from AquariusZi (via @davideneco), who is a well-known name in the tech scene in the PTT forums. He was also the first to write about the expected die sizes of AMD’s RDNA-2 GPUs.
The source also refers to the launch in November 2020 and also mentions that there are no orders for the Navi-GPU yet, which indicates that there will only be reference cards at the launch, but no board partner cards. This coincides with my information that the board partners have not even received technical documentation for the design yet and even a bill of material is said to be a long way off. I myself had already written about this several times.
While AMD is keeping the board partners (for whatever reason) on such a short leash, Ampere is already in the wild, and there are probably already some board partner designs that are supposed to go through my article “Nvidia’s Rules and AMD’s Protectionism – Clever Quality Management, Profit Maximization and Niche Manufacturers – Behind-the-scenes Insights”. However, it has not yet been possible to find out at what stage they are at. However, I can confirm from my own sources that the most recent key data for the amp models should be correct.
The second piece of information relates to the memory design, and the source says that the next RDNA-2 GPUs, at least the consumer cards, will not get HBM2 memory or the 2.5D design required for it. In the past, it was already widely reported that Radeon RX graphics cards based on Big Navi GPUs would have 16 GB of GDDR6 memory together with a 512-bit memory interface. This would approximately double the memory capacity and bus size compared to Navi 10.
At the same time, there may well have been indications in AMD’s GPU drivers that there was HBM2 memory for AMD’s big nav GPUs. Discovered by FreeDesktop (via Videocardz) it is mentioned that a 2048 bit bus interface could exist, but this would suggest two variants of the Big Navi chip, because HBM2 memory requires a 2.5D design, which leads to a very different chip design due to the different memory controllers.
It’s more likely that AMD will retain GDDR6 memory for its next-generation RDNA2 consumer graphics cards, but there may well be a parallel workstation or prosumer version with HBM2 memory that could be derived from the MI cards. But this already belongs to the culinary world of Spekulatius & Co.
The node for the RDNA 2 GPUs is also still a bit unclear, because while AMD has already confirmed 7nm+ for Zen 3, the RDNA 2 GPUs have only been run in conjunction with the 7nm node since the earliest roadmap. However, AMD has since pointed out that 7nm, like the updated roadmap for Zen CPUs, does not mean that 7nm might not be an improved version of the node. According to AquariusZi, AMD’s flagship and mainstream RDNA-2 GPUs will also use TSMC’s enhanced 7nm+ process node.
The table above shows the possible specifications of the new card compared to its predecessors. In addition to all the rumors, Rogame also managed to extract the latest GPU configuration for the Big Navi chip from the software. For the GPU, this also refers to 80 computing units with a total of 5120 cores and occupies the data recorded in the table:
Another rumor looks at AMD’s next-generation RDNA 3 GPUs and mentions that the GPU is currently in the early design and testing stages, but will have the most revolutionary GPU design in the form of a chipset architecture. The RDNA-3 chips will offer the same design methodology as Zen 2, but for GPUs, allowing AMD to combine multiple GPU IPs. In this context, I would like to refer you to my article “Another and bigger Navi chip? First indications of a possible multi-chip package!”, where I already mentioned this in June, but was only mildly smiled at in the usual forums.
Mentioned in this context is also the “Advanced Node”, where AMD could use several different nodes for the different chipplets embedded on the same interposer. It is likely that AMD separates the graphics dies from the I/O dies, analogous to the current CPUs. However, speculating about the point in time of market maturity is taking things a little too far.