MSI SPATIUM M480 Pro 2 TB NVMe SSD in review – Is the SSD with the “Pro” in the name better than the one without?

1 - Intro, unboxing, technical data 2 - Teardown: Controller and NAND in detail 3 - Dynamic pSLC cache in detail 4 - Test system and synthetic tests 5 - Application benchmarks and conclusion

I had already written it that the SSD can or should be cooled via the motherboard (or its own passive or active cooler) and then also stays a bit cooler, because the NAND also acts a bit more restrained and the heat conduction connection fits. Once you have removed the stickers, you can see the PCB, which is no longer TECHVEST, but is at least pin-compatible with the “Play”. You can see the memory, the controller and the DRAM modules.

But always nice one after the other, we start best with the controller. The used PS5018-E18 from Phison was developed from scratch and is manufactured in TSMC’s 12 nm node. It is, in terms of features and performance, a very interesting and fast PCIe 4.0 x4 SSD controller. To make it happen, Phison has included five Arm Cortex R5 CPU cores, three of which act as primary cores for the main tasks, while the other two are clocked lower for the Dual CoXProcessor 2.0 code to take at least some of the load off the three main cores as a more economical tandem.

The controller communicates with the NAND via eight NAND flash channels at up to 1,600 MTps and supports capacities of up to 8 TB with 32 chip enable. Our SSD contains eight NAND modules, four on each side, thanks to the small size of the controller, which measures just 12 x 12 mm. The design also uses a DRAM-based architecture, with the Spatium M480 Pro again containing two DDR4 chips from SK hynix, one on each side of the PCB. These are each 8 GB modules in the form of the H5AN8G6NCJR, which is CMOS Double Data Rate IV (DDR4) Synchronous DRAM.

Phison’s PS5018-E18 complies with the NVMe 1.4 specification and has a number of common features. For example, it supports both Trim and S.M.A.R.T. Like other controllers, it uses Active State Power Management (ASPM), Autonomous Power State Transition (APST) and L1.2 ultra-low power state (see datasheet page 1). Thermal throttling is implemented, but is of no further concern, as the controller does not get too hot in most applications. This can also be seen in the fact that, in contrast to the older models like the E16, an integrated nickel heatsink can be dispensed with.

It also uses the fourth-generation LDPC ECC engine, SmartECC (RAID ECC) and end-to-end Data Path Protection for robust error correction and improved data reliability. It even supports hardware-accelerated AES 128/256-bit encryption (which is TCG, Opal 2.0 and Pyrite compliant) and has a built-in crypto-erase function. Phison’s E18, like the E12S and E16 models, supports fully dynamic write caching. The size of the dynamic pSLC cache, which I will discuss in a moment, is therefore 1/3 of the available capacity of the TLC drive. Phison has also implemented SmartFlush, which enables fast cache recovery for predictable and consistent performance. So much for the theory. Well, not quite.

Micron’s 176-layer TLC 3D NAND (codenamed B47R)

The Phison PS5019-E19T just described is compatible with a wide range of flash memory variants and supports modern NAND chips with 1200 MHz interfaces. And because it’s so nicely compatible, if you’re a low-cost NVMe SSD vendor, you can also use Micron’s latest 176-layer TLC 3D NAND (codenamed B47R) with it. Thus, the MSI Spatium M450 I tested contains two IABHG94AYA chips with eight 512-gigabit TLC 3D NAND blocks each inside.

By the way, Micron’s still quite new 176-layer flash is the first real in-house development by Micron after the separation from Intel. This memory also differs very clearly in its inner structure from the products of all other manufacturers. The cell structure of the Micron NAND relies on replacement gate, which in the end is a cross between floating gate and charge trap technologies. Micron replaced the polysilicon in the gate material with metal in this NAND and switched to a different process for etching the vertical cylindrical channel, resulting in an increased diameter.

In addition, a non-conductive layer of silicon nitride has been introduced into the structure of the micron memory where data can be stored. This layer also quite effectively reduces mutual interference between the cells in such a vertical stack. Of course, we can go into a bit more detail. The next figure shows a chip with a view of the metal top side, a chip with a view of the CMOS circuits (CuA) and the markings of the B47R chip. Compared to the older B37R TLC die, the chip size has been reduced by a whopping 25% due to the higher cell density, larger number of 3D NAND cells and effective scaling of the design. The B47R is now Micron’s second generation CTF die after the B37R.

The height of the NAND cell array (for comparison, the height from the selector on the source side to the BL) is now more than 11 µm. The total number of gates, including selectors (STs) and dummy word lines (DWLs) per vertical NAND strand is 195, so-called 195T, which is the highest number ever achieved in 3D NAND. They rely on double-stack architecture, replacement gate process, charger trap nitride (CTN) and CMOS-under-array (CuA) techniques. The bit density reaches 10.273 Gb/mm2 for the 512Gb TLC die.

Thus, in the end, it was possible to achieve a number of positive effects, because it was possible to increase the speed of the programming cells, increase their stability, reduce power consumption and at the same time also improve the reliability of data storage. Ultimately, Micron’s 176-layer TLC 3D NAND thus takes the next step in 3D flash technology in general. And in terms of performance, Micron claims that the new memory has reduced read and write latency by about 35% compared to the previous generation 96-layer memory. Well..