Sometimes you can’t keep up with the news at all, because two more Engineering Samples (ES) have turned up, whose OPN contains interesting details about the targeted clock rates. These two OPNs also stand for the new 16-core CPUs CPUs from the already known B0-Stepping. Whether the faster of the two will be called Ryzen 9 4950X or 5950X (or something completely different), in order to be on par with the APUs in the nomenclature, is still open.
100-000000065-04_46/36_Y
100-000000061-06_49/37_Y
The faster of the two samples now boosts to 4.9 GHz, while the base clock is set to 3.7 GHz. In contrast to the previous ES, this is another visible increase and shows that you probably also slowly fight your way towards the 5 GHz mark at the boost clock. Whether this psychological and especially for marketing so important brand will be cracked is still open. But at least with this ES the next step has been taken. From one of the slower ES could then perhaps also emerge the Ryzen 9 4950 / 5950 without X, which is certainly needed in the portfolio.
Also interesting on this topic
Exclusive Leak about AMD’s next CPU generation: “Ryzen 9 4950X” Vermeer with higher boost clock and new features á la Intel
New X86 features for Vermeer (VMR)
But it is not only the beat that is changing, as more and more details are becoming known about the technology. With ERMS and FSRM, AMD is now finally introducing, with some delay, two functions that Intel will already have introduced in 2013 (ERMS) and 2009 (FSRM). 2017 (FSRM) to improve the performance of its own CPUs. The fact that AMD is only now catching up shows that they are fighting for every improvement on a broad front and try to compensate for every disadvantage, no matter how small.
ERMS = Enhanced Repeat Move String
FSRM = Fast Short Repeat Move String
With the new Zen3 CPUs, Fast Short REP MOV (FSRM) is finally added to AMD’s CPU functions analog to Intel’s X86_FEATURE_FSRM. Intel had already introduced this in 2017 with the Ice Lake Client microarchitecture. But now AMD is obviously using this feature to increase the performance of REP MOVSB for short and very short operations. This improvement applies to Intel for string lengths between 1 and 128 bytes and one can assume that AMD’s implementation will look the same for compatibility reasons. usually you even coordinate your actions.
As early as 2013, Intel decided to make a major revision to REP MOVS and implemented the CPUID ERMSB bit (Enhanced REP MOVSB) to indicate that the CPU could handle byte-sized motion and memory instructions quickly and efficiently. In addition to adding FSRM to the x86 feature code, ERMS is therefore also very interesting, as it allows the bandwidth to be increased considerably, which is a not inconsiderable advantage and logically complements FSRM.
Simplified it can be rewritten so that the MOVS command copies data from one memory area to another. If you now prefix the MOVS command with the prefix REP, this command is repeated as long as you specify it before. However, unlike FSRM, ERMS mainly concerns larger blocks from 256 bits upwards and must always be forward looking. However, ERMS also has a major disadvantage, as it requires a few cycles to be run first (startup latency). Depending on the size, FSRM may be the better alternative for smaller operations.
Of course all this is also operating system dependent and must be implemented in the kernel first. But since Intel has already been using this for years, AMD should be able to break down open doors with Vermeer.
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