binary. I use hexdump instead of cat.sollte in hex bzw binary sein.
binary. I use hexdump instead of cat.sollte in hex bzw binary sein.
uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL
uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable)
@Veii scheint die kurve entschlüsselt zu haben.
Nun hab ich es korrektDas bestätigt das die rdna2 kurve nichts mit der alten Formel zu tun hat.
f(x)=a·x²+b·x+cNun hab ich es korrekt
Mehr ein wenig später mit weniger halbwissen
Was wäre diese "alte Formel" ?
Es ist PLL droop & AVFS balancing , auf PSM-Margins. Ne Zwiebel
.... mein Sommersetting für die 6800 ist jetzt bei ca. 109W avg. (tgp) bei nem PL von 153W (tgp)
just for fun, komme jetzt auch ohne Taktbegrenzung im Gravity auf Wattspitzen nahe am PL=115W (tgp), ... durch PL=-8 !?Mit der RX6900XT und dem langsamsten Profil (Taktbegrenzung) bei rund 100-107Watt schaut es schon völlig anders aus.
Thanks, l've looked at it. Indeed, clock source is DFLL and prefered droop model is piecewise linear (correct offset for the GfxclkSource is 0x0680 ).Hex is just another way to look at binary data. 4 bits (binary digits) are one digit in hexadecimal.
To your question, i can't give you a complete answer. But i can give you some data here..
the offset of this byte is 0x67FCode :uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL
this one would be at offset 0x734Code :uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable)
Update:
Beide Bytes sind (noch) nicht im MPT inbegriffen, werde ich mal auf die Liste setzen. Wenn ihr schon damit experimentieren wollt, Hexeditor (ich kann HxD empfehlen) nutzen, .mpt-Datei laden und dort aufs Offset nochmal 0x100 dazu zählen. Speichern, ins MPT laden und in die Registry schreiben oder Registry-Datei erstellen. Alle nicht im MPT anwählbaren Daten bleiben selbstverständlich erhalten.
typedef struct {
uint16_t GfxclkFmin; // MHz
uint16_t GfxclkFmax; // MHz
QuadraticInt_t CustomGfxVfCurve; // a: mV/MHz^2, b: mv/MHz, c: mV
uint16_t CustomCurveFmin; // MHz
uint16_t UclkFmin; // MHz
uint16_t UclkFmax; // MHz
int16_t OverDrivePct; // %
...
int16_t VddGfxOffset; // in mV
...
} OverDriveTable_t;
Thanks, Alas! )Give it time and i'll put a more technical writeup out
If friend is not faster.
Damn, it took me a while to realize you're talking about ADL, and not amdgpu, lol.RDNA1 has the OD8_GFXCLK_CURVE feature enabled, where the RDNA2 only has OD8_GFXCLK_FMAX / OD8_GFXCLK_FMIN to set
OD gfx min/max is there in navi10 headers, I believe they're just ignored if related feature is disabled:I don't know what the driver makes of it, but i guess the min/max is the way to go for RDNA2, i wouldn't want to force it back to RDNA1 methods.
static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
...
switch (type) {
case PP_OD_EDIT_SCLK_VDDC_TABLE:
if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
return -ENOTSUPP;
}
if (!table_context->overdrive_table) {
dev_err(smu->adev->dev, "Overdrive is not initialized\n");
return -EINVAL;
}
...
Yeah, it works fine, and would definitely fit as the MPT upgrade.with MCU you can edit the actual settings for the driver
Another friendThanks, Alas! )
Is your friend Sam Naffziger by any chance?
Is Quadratic Model , or SpeedShift model ?f(x)=a·x²+b·x+c
I beleive other three is either legacy/backup or for the not yet released SKUs.Makes me wonder why AMD has to implement 4 DFLL models
Can you tell me a bit more on the BTC topic. I struggle to understand 4 thingsI beleive other three is either legacy/backup or for the not yet released SKUs.
If I get it right, current AVFS model actually don't need any fuses and their BTC correction with some quadratic transfer function for each voltage island, since DFLL together with the adaptable voltage margin approach solves most of the problems, such as VFT variation and AC noise dependency, and other timing issues.
Later/Default value is "per-sku based".I beleive other three is either legacy/backup or for the not yet released SKUs.
DpmDescriptor_t DpmDescriptor[13];
typedef struct {
uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only
uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used
uint8_t Padding;
LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
typedef struct {
uint32_t m; // store in IEEE float format in this variable
uint32_t b; // store in IEEE float format in this variable
} LinearInt_t;
QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V)
typedef struct {
uint32_t a; // store in IEEE float format in this variable
uint32_t b; // store in IEEE float format in this variable
uint32_t c; // store in IEEE float format in this variable
} QuadraticInt_t
uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin
uint16_t Padding16;
} DpmDescriptor_t;
Where did you see "GFX DFF BTC"? Have never seen that. FLL is common term, DFLL - is fully digital frequency locked loop.Can you tell me a bit more on the BTC topic. I struggle to understand 4 things
GFX DFF BTC
FLL BTC for L3
FLL itself for resume
& DC BTC as a functionality/sensor itself
It follows PSM Margins. Has a fixed range
And appears that many voltage values depend on it
DC BTC is odd,, i miss information
Too much bitcoin search results to figure out it's real usage)
EDIT:
Soo, DC-, tolerance & bus tie contactor
Both droops based on voltage islands of AVFS ~ withing margins allowed ?
Higher value, more constant supply?)
You surely know what a bus tie contactor does ?
I thought it is SpeedStep or SmartShift"SS" means "Slow-slow curve (GHz->V)" in AMD language.
I'm not exactly confident on it, as all i find about DFLL and PLL ~ have to do with ext clock crystalsDC Tolerance may refer to additional gb gained relative to AC ones defined at ATE, but I'm not sure.
What does DfllModel 3 mean? Per part piecewise linear? The same as for the Navi 23.Take a look at this dump
Model 3 is undocumented,What does DfllModel 3 mean? Per part piecewise linear? The same as for the Navi 23.
I don't think Navi 23 is allowed to use piece-wiseThe same as for the Navi 23.