AMD Zen 6 leak cites 12 cores per CCD and 48 MB of L3 cache with virtually unchanged chiplet area

Sometimes it’s not the big presentations with lots of stage fog, but a few dry figures from the rumor mill that deserve more attention. That’s exactly what happened with AMD Zen 6. A new leak describes a CCD with 12 CPU cores and 48 MB of shared L3 cache per chiplet, while the die area is reportedly only slightly larger than Zen 5’s. None of this has been officially confirmed. That’s precisely why the report is interesting, because it touches on an area where AMD has been remarkably disciplined for years: eight cores and 32 MB of L3 per classic desktop CCD were practically considered set in stone. If that changes, it wouldn’t be a cosmetic update, but a significant shift in AMD’s chiplet architecture.  The basis for the current report is a post published by HXL that has been picked up by several tech news outlets. The key takeaway can be summarized quickly: Zen 6 is said to combine 12 cores and 48 MB of L3 cache on a single CCD, with only a moderate increase in die area. Citing the leak, Tom’s Hardware mentions a figure of around 76 mm² and classifies this as a relatively small increase compared to Zen 5. However, this remains merely a leak—not a specification confirmed by AMD, nor a reliable product announcement. At this stage, it is therefore essential to clearly distinguish between a plausible early indication and a verified technical specification. 

This distinction is particularly important because AMD itself has so far only confirmed the broad outline. Officially, it is established that the next EPYC generation, “Venice,” is based on Zen 6 and is scheduled to launch in 2026. AMD has also already announced that “Venice” is built on TSMC’s N2 technology and is intended to be the next major step in server technology. What AMD has not officially stated, however, is how many cores a classic Zen 6 client CCD will feature, how large its L3 cache will be, or whether the now-rumored 12 cores apply directly to desktop products like “Olympic Ridge.” This is precisely where the speculation begins. 

Technically, however, the move would be logical. According to AMD, Zen 5 in Granite Ridge operates with up to two CCDs, each with eight cores and 32 MB of L3 cache per CCD. This basic structure is also clearly visible in the Hot Chips material on Zen 5: eight cores per complex, 32 MB of L3 per CCD. If Zen 6 does indeed move to 12 cores and 48 MB of L3 per CCD, the ratio of cores to cache per core would remain remarkably consistent. AMD would then not only add cores but also scale the cache layout proportionally. This suggests a structured expansion of the familiar CCD principle rather than a completely radical break from the previous approach. The truly exciting point, therefore, isn’t even the raw number “12,” but the efficiency behind it. If AMD manages to implement a 12-core CCD with 48 MB of L3 cache on an area that, according to the leak, is only slightly larger than Zen 5, this would have direct implications for yield, segmentation, and product planning. At the desktop level, classic 12-core processors would then no longer necessarily rely on two partially disabled CCDs, but could instead be implemented as a single-chiplet solution. A 24-core processor on two fully expanded CCDs would suddenly no longer be an exotic idea in the mainstream, but rather a fairly logical high-end configuration. Mind you, all of this is speculation at this stage, not confirmation. The figures from the leak suggest this direction, but AMD itself has not yet publicly endorsed them.

The fact that such information is surfacing right now also fits the timeline. Just a few days ago, early entries regarding Zen 6-based EPYC “Venice” engineering samples became public. Tom’s Hardware reported on variants with significantly increased core density in the server environment, including configurations with up to 192 cores and new CCD layouts for Zen 6c. This does not serve as proof of consumer Zen 6 CCD structures, but it does show that AMD is clearly aiming for higher density and stronger scaling with Zen 6 overall. Against this backdrop, a larger client CCD no longer seems like an outlier, but rather like the smaller sibling of a broader architectural strategy. 

For the desktop market, this would be a highly significant shift. Since Zen 2, AMD’s mainstream logic has relied heavily on a CCD supporting eight cores in its full configuration. Many product tiers, from Ryzen 7 to Ryzen 9, ultimately depend on this building block. If this base unit comprises 12 cores instead of 8 in the future, the entire foundation of the model hierarchy will automatically shift. Then we’re no longer just talking about slightly higher IPC, slightly higher clock speeds, and the usual “up to” claims, but about a new balance between manufacturing costs, core count, and cache configuration. That’s exactly why this leak is more interesting than many of the usual clock speed or naming rumors. It targets the architecture itself, not just the label. However, almost everything that we’d ideally like to have confirmed for a finished report remains unclear. There is no official AMD statement regarding a Zen 6 desktop launch, no confirmed model names for consumer products, and no verified information on whether the 12-core/48-MB configuration is intended to be standard across the Ryzen lineup or was initially just a development target. The often-expressed hope for particularly large X3D configurations also remains speculation for now. It would therefore be premature to draw conclusions about mass-produced products based on a leak regarding a base chiplet. As things stand, the discovery primarily confirms that AMD is internally or within early circles associated with precisely this interpretation. Nothing more, but also nothing less. 

Conclusion

The Zen 6 leak is remarkable precisely because it doesn’t scratch the surface, but rather touches on the foundation of AMD’s chiplet approach. Twelve cores and 48 MB of L3 per CCD would not be a minor evolutionary step, but a change with real consequences for the entire Ryzen lineup. This isn’t official yet, and that’s exactly how it should be treated. But the direction seems plausible: more density, more flexibility, and a CCD designed to handle significantly more without bursting at the seams. If this is confirmed, then Zen 6 would not only be the next architecture, but also the next definition of what AMD considers “normal” in the mainstream. And that’s where it gets interesting, because such changes ultimately have a greater impact than any PR slide with percentage figures that no one wants to look at three months later anyway. 

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